#P10619. [ICPC2013 WF] Harvard
[ICPC2013 WF] Harvard
题目背景
题目描述
The term “Harvard architecture” applies to a computer that has physically separate memories for instructions and data. The term originated with the Harvard Mark I computer, delivered by IBM in 1944, which used paper tape for instructions and relays for data.
Some modern microcontrollers use the Harvard architecture – but not paper tape and relays! Data memory is organized in banks, each containing the same number of data items. Each data-referencing instruction has a byte offset to a bank, and a bit that is used to select the bank to be referenced. If is , then bank is referenced. If is , then the value in a bank select register (BSR) identifies the bank to be used. Assume each instruction takes the same time to execute, and there is an instruction that can set the BSR’s value.
For example, suppose there are banks of bytes each. To access location , either use a single instruction with and , or set the BSR to in one instruction and then use an instruction with and . The first approach is faster since it does not require setting the BSR.
Now suppose (with the same memory) the location to access is . Only one approach will work here: execute an instruction that sets the BSR to (unless the BSR already has the value ) and then use an instruction with and .
A program is a sequence of operations. Each operation is either
- a variable reference, written as V, where is a positive integer, or
- a repetition, written as R
<program>
E, where is a positive integer and<program>
is an arbitrary program. This operation is equivalent to n sequential occurrences of<program>
.
Your problem is to determine the minimum running time of programs. In particular, given the number and size of the memory banks and a program to be executed, find the minimum number of instructions (which reference memory location and possibly set the BSR) that must be executed to run the program. To do this you must identify a mapping of variables to memory banks that yields the smallest execution time, and report that execution time – that is, the number of memory references and BSR register settings required. The BSR’s value is initially undefined, and changes only when an instruction explicitly sets its value.
输入格式
The input consists of a single test case. A test case consists of two lines. The first line contains two integers and , where is the number of memory banks and is the number of variables that can be stored in each memory bank. The second line contains a non-empty program with at most space-separated elements (each R, V, and E counts as one element).
You may assume the following:
- In a repetition R, the number of repetitions satisfies .
- In a loop operation R
<program>
E, the loop body<program>
is not empty. - In a variable reference V, the variable index satisfies .
- The total number of variable references performed by an execution of the program is at most .
输出格式
Display the minimum number of instructions that must be executed to complete the program.
题目大意
【题目描述】
“哈佛架构”一词适用于指令和数据具有物理上分开的存储器的计算机。该术语起源于哈佛 Mark I 计算机,由 IBM 于 1944 年交付,该计算机使用纸带作为指令,使用继电器作为数据。
一些现代微控制器使用哈佛架构——但不使用纸带和继电器!数据存储器被组织成多个存储区(bank),每个存储区包含相同数量的数据项。每条引用数据的指令都有一个字节偏移量 和一个位 ,用于选择要引用的存储区。如果 为 ,则引用存储区 。如果 为 ,则在存储区选择寄存器(BSR)中的值标识要使用的存储区。假设每条指令执行时间相同,并且存在可以设置 BSR 值的指令。
例如,假设有 个存储区,每个存储区有 个字节。要访问位置 ,可以使用 和 的单条指令,或者在一条指令中将 BSR 设置为 ,然后使用 和 的指令。第一种方法更快,因为它不需要设置 BSR。
现在假设(使用相同的存储器)要访问的位置是 。这里只能使用一种方法:执行一条指令将 BSR 设置为 (除非 BSR 已经是 ),然后使用 和 的指令。
程序是操作的序列。每个操作可以是
- 变量引用,写作 V,其中 是正整数,或
- 重复,写作 R
<program>
E,其中 是正整数,<program>
是任意程序。此操作相当于<program>
的 n 次连续出现。
你的任务是确定程序的最小运行时间。具体来说,给定内存存储区的数量和大小以及要执行的程序,找出必须执行的最小指令数(引用内存位置和可能设置 BSR),以运行程序。为此,你必须确定将变量映射到存储区的方式,以产生最小的执行时间,并报告该执行时间——即完成程序所需的内存引用和 BSR 寄存器设置的数量。BSR 的值最初未定义,仅在指令显式设置其值时更改。
【输入格式】
输入包含一个测试用例。测试用例包含两行。第一行包含两个整数 和 ,其中 是存储区的数量, 是每个存储区可以存储的变量数。第二行包含一个非空程序,最多包含 个用空格分隔的元素(每个 R, V 和 E 都算作一个元素)。
你可以假设以下几点:
- 在重复 R 中,重复次数满足 。
- 在循环操作 R
<program>
E 中,循环体<program>
不为空。 - 在变量引用 V 中,变量索引满足 。
- 程序执行的总变量引用数最多为 。
【输出格式】
显示完成程序所需执行的最小指令数。
翻译来自于:ChatGPT。
1 2
V1 V2 V1 V1 V2
5
2 1
V1 V2 V1 V1 V2
6
1 2
R10 V1 V2 V1 E
30
4 1
V1 R2 V2 V4 R2 V1 E V3 E
17